Logic Gates

Boolean Algebra & Visualizer

Settings

Select Logic Gate:

Inputs

Input A (0)

Input B (0)

Input C (0)

Output

0

CMOS Transistor & Logic Gate Handbook

Mathematical Principles & Theorems

Models transistor-level implementation of digital logic gates using Complementary Metal-Oxide-Semiconductor (CMOS) technology. CMOS logic combines a Pull-Up Network (pMOS transistors, conductive when gate voltage is LOW / 0) and a Pull-Down Network (nMOS transistors, conductive when gate voltage is HIGH / 1). Inverter requires 1 pMOS and 1 nMOS; 2-input NAND requires 2 parallel pMOS and 2 series nMOS transistors.

Operating Instructions

Select gate topology: NOT (Inverter), NAND, NOR, AND, OR, XOR.
Toggle input terminal voltages (A and B) between 0V (Logic 0) and Vdd (Logic 1).
Trace active current conduction paths through the pMOS and nMOS transistor networks.
Verify the output voltage level and corresponding Boolean truth table row.